View L6452_326488.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
L6452
DUAL 13X16 MATRIX HEAD INK JET DRIVER
DRIVES TWO 13X16 MATRIX HEADS HEAD TEMPERATURE SENSING POWER UP SYSTEM ELECTRICAL NOZZLE CHECK 8 BIT A/D 5 BIT D/A 4KV ESD PROTECTED OUTPUTS DESCRIPTION L6452 is a device designed to drive two 13x16 matrix ink jet printheads in printer applications. The output stage is able to source simultaneously 400 mA on each of the 16 power lines (columns) with a duty cycle of 33% in normal printing and 66% in head pre-heating. On the address lines (rows), the load is only capacitive (MOS FET driving capability). The driver can control two printheads, but only one is active at a time. The address scanning counter is included and can be disabled to allow a different scanning scheme. Figure 1. Block Diagram
PQFP100
In order to avoid output activation during the supply transient, an internal power-up system is implemented. As supporting function, L6452 is capable of sensing the head silicon temperature and to electrically check each nozzle. The device is also integrating a thermal protection.
POWER & LOGICAL SUPPLIES PRINT HEAD DRIVER
16 POWER LINES
CONTROL LINES
13 ADDRESS LINES CHANNEL A
PRINT HEAD A
13 ADDRESS LINES CHANNEL B
PRINT HEAD B
A/D & PRINT HEAD TEMPERATURE CONTROL LINES
PRINT HEAD TEMPERATURE CONTROL
ANALOG INPUTS
D97IN523
March 1999
1/16
L6452
PIN CONNECTION (Top view)
STEPUP_GND STEPUP_BO _ONENABLE VSTEP-UP CRCLOCK
CRDATA
CS_GND
RESCS1
CLKCS0
_ENCH
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CRLATCH OUTPUT15 VC POWGND OUTPUT14 OUTPUT13 VC OUTPUT12 OUTPUT11 VC OUTPUT10 OUTPUT9 VC OUTPUT8 POWGND OUTPUT7 VC OUTPUT6 OUTPUT5 VC OUTPUT4 OUTPUT3 VC OUTPUT2 OUTPUT1 VC POWGND OUTPUT0 LATCH_CLEAR NCEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D97IN489B
CHSEL
UPC52
VXb
VXa
REXT
RXA
RXB
VDD
S3
Va
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
ENLC GND HSA1 HSA2 HSA3 HSA4 HSA5 HSA6 HSA7 HSA8 HSA9 HSA10 HSA11 HSA12 HSA13 Vr HSB13 HSB12 HSB11 HSB10 HSB9 HSB8 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 GND
LATCH_DATA
LONG_PULSE
ADCGND
_RESET
CONV_START
ANALOGND
CH0_BUF
ADDATA
NCOUT
Va
CH5
CH4
CH3
CH2
SHORT_PULSE
SDC
PIN FUNCTIONS
Pin # 1 2, 5, 6, 8, 9, 11, 12, 14, 16, 18, 19, 21, 22, 24, 25, 28 3, 7, 10, 13, 17, 20, 23, 26 4, 15, 27, 51, 79, 92 29 2/16 Name CRlatch Output 15...0 Function A rising edge latches the information present into the control register High side DMOS outputs. To be active, Short Pulse and/or Long Pulse and Nozzle Check Enable must have a low level
Vc
Outputs Power Supply
GND Latch Clear
logic and power ground A high level resets all bit in the latch
ADCK
VREF
CH1
SDI
L6452
PIN FUNCTIONS (continued)
Pin # 30 Name NCEn Function A high level enables the internal current sources and disables all DMOS outputs. To be active, the internal current sources must have their corrsponding bit set in the 16 bit latch and Long Pulse must be set to low level. A low level enables the internal HSA/B short circuit detection A rising edge latches the 16 bit stored in the shift register in the 16 bit latch Serial data input of the shift register The data bit presented to the Serial Data Input pin is stored into the register on the rising edge of this pin A low level activates all outputs having their coresponding bit in the 16 bit latch set (this pin has an internal pull-up resistor) A low level activates all outputs having their coresponding bit in the 16 bit latch reset (this pin has an internal pull-up resistor) A low level disables all functions and clears all registers A high level enables the A/D to start the new conversion A/D clock signal; the ADDATA signal are valid on the falling edge of this pin If Nozzle Check Enable is high this output provides a high level when the open load is detected on the output. If Nozzle Check Enable is low this output provides a high level when a short circuit is detected on HSA/B output Analog output signal (CH0 buffered) A/D serial data output Analog ground connection Ground of internal ADC Power supply Reference voltage generator A/D input signals Head selector address output channel B Head Select Power Supply Head selector address output channel A A high level enables the counter and the internal decoder will activate of the HSx outputs according to the counter's outputs. Signal S0 becomes Clock Counter and S1 becomes Reset Counter A low level enables channel A and a high level enables channel B Decoder input signals when Enable Counter is low A high level enables the internal counter to up counting. A low level enables down counting A low level resets the internal counter A low level enables the selected channel (this input has an internal pull up resistor) A high level clocks the internal counter Ground of step up block Boost voltage Driving voltage of power DMOS stage 5V logic supply An external resistor connected versus ground fixes the internal current source value Current source outputs RxA, RxB voltage after an optional external filter A low level enables the current source generator according the _A/B and ON/_OFF control register bit Data on pin CRdata are stored into the register on the rising edge of this pin Control register serial data input 3/16
31 32 33 34 35 36 37 38 39
Latch Data SDI SDC Long Pulse Short Pulse _Reset ConvStart ADCK NCOut
40 41 42 43 44, 90 45 46 to 50 52 to 64 65 66 to 78 80
CH0_buf ADDATA AnalogGND ADCGND Va Vref CH5..CH1 HSB1..HSB13 Vr HSA13..HSA1 EnlC
81 82 83 84 85 86 87 88 89 91 93 94, 95 96, 97 98 99 100
ChSel S3 UpC/ S2 ResC/S1 _EnCh ClkC/S0 Step up GND Step up boost Vstep up VDD Rext RxB, RxA VxA, VxB _ONenable CRclock CRdata
L6452
Figure 2. Block Diagram: Nozzle activation part.
* LONG PULSE * SHORT PULSE OUTPUT 0 OUTPUT 1 OUTPUT 2 OUTPUT 3 OUTPUT 4 OUTPUT 5 16 BIT SERIAL INPUT & PARALLEL OUTPUT OUTPUT 6 16 BIT LATCH 16 POWER OUTPUT STAGES OUTPUT 7 OUTPUT 8 OUTPUT 9 OUTPUT 10 OUTPUT 11 OUTPUT 12 OUTPUT 13 OUTPUT 14 OUTPUT 15 SERIAL DATA INPUT SERIAL DATA CLOCK LATCH CLEAR LATCH DATA NOZZLE CHECK ENABLE NOZZLE CHECK OUTPUT
HSA 1 HSA 2 HSA 3 HSA 4 HSA 5 13 MOS DRIVERS CHANNEL A 0 to 13 UP/DOWN COUNTER HSA 6 HSA 7 HSA 8 HSA 9 C0 HSA 10 HSA 11 HSA 12 4 to 13 LINES DECODER HSA 13
C1 SELECTOR
ENABLE INTERNAL COUNTER SEL 3 UP COUNTING/SEL 2 *RESET COUNTER/SEL 1 CLOCK COUNTER/SEL 0
C2
HSB 1 HSB 2 HSB 3 HSB 4 HSB 5 13 MOS DRIVERS CHANNEL B HSB 6 HSB 7 HSB 8 HSB 9 HSB 10
C3
*SELECT CHANNEL *ENABLE CHANNEL
D97IN524
HSB 11 HSB 12 HSB 13
4/16
L6452
Figure 3. Block Diagram: Power Line Output Stage.
POWER SUPPLY 10mA
DATA BIT 0 1 0
OUTPUT 0
DATA BIT 1 FROM 16 BIT DATA LATCH
OUTPUT 1
DATA BIT 15
*LONG PULSE * SHORT PULSE TRIGGER NOZZLE CHECK ENABLE
D97IN525
OUTPUT 15
NOZZLE CHECK OUTPUT
5/16
L6452
ABSOLUTE MAXIMUM RATINGS
Symbol Vc Vr Va Vdd Vstep_up Vin Iout Tj Tamb Tstg Parameter Power line supply voltage Address line supply voltage Analog supply voltage Logic supply voltage Driving voltage of power DMOS stage Logic input voltage range Output continuous current Junction temperature Operating temperature range Storage temperature range Value 14 14 14 6 28 -0.3 to Vdd+0.3 0.5 150 0 to 70 -55 to 150 Unit V V V V V V A C C C
DC ELECTRICAL CHARACTERISTICS (Tj = 25C)
Symbol Vc Vr Va V dd Ics Irs Ias Ic Ir Ia Idd Vref Irefext Icss Icss/Icss Vampout V cm g1 g2 Vstep-up Parameter Power Line Supply voltage Address line supply voltage Analog supply voltage Logic supply voltage Vc sleep supply current Vr sleep supply current Va sleep supply current Vc supply current Vr supply current Va supply current Vdd supply current Reference Voltage Reference current (external) Programmed constant current Constant current regulation Output voltage of integrated amplifier Operating input voltage at pins Vxa and Vxb Amp. A1 Voltage gain Amp.A2 Voltage gain Driving Voltage of power DMOS Test Condition * * * ONenable = 1 Reset = 0 Min. 10.5 ** 10.5 10.5 4.5 Typ. 11.5 11.5 11.5 5 Max. 12.5 12.5 12.5 5.5 1 0.3 3 1.5 0.6 13 5 5.15 7 13.5 Unit V V V V mA mA mA mA mA mA mA V mA mA % V V
IRext = 3mA sleep or normal condition Tamb = 5 to 55C Iccs = Vref 4 Tamb = 5 to 55C
4.85
5 12 0.33
2Rext
Va =11V
e *** Vref = 5V g1=1.2 g2=3 1.188 2.95 1.2 3.02 Vc +11
Va-1 7 1.212 3.10
V
* the three supply voltage are independent inside the specified value; ** the Min value for Vc Power line could be decreased up to 9V (under evaluation); *** e = 2 Vstep
A/D CONVERTER A/D input voltage V A/D in
I exch
A/D input current
Selected Channel: CH1toCH5 Selected Ch=CH0 Input CH1 to CH5 Channel selected or not Vref = 5V Vref = 5V Any step N>=4
0 e ***
Vref Vref 1
V V A
OFFSET VOLTAGE GENERATION / DAC Voffset Offset Voltage Voltage increment (1LSB) Vstep Voffset/Vref Kdac
2.5+ e*** 156
7.34 3
V mV %
6/16
L6452
DC ELECTRICAL CHARACTERISTICS (Tj = 25C)
Symbol Parameter A/D CONVERTER TIMINGS Conv. start set up time Tcscks Conv. Start hold time T csckh Falling edge of clock to data Tckou t out valid delay ConvStart falling edge to output Tcsz in Hi-Z delay Clock frequency Fadck Conv. Start low level time Tcslow Theoretical acquisition time Tacq th Real acquisition time Tacq pr DIGITAL INTERFACE INPUT Schmitt Trigger positive-going V inp Threshold Schmitt Trigger negative-going Vinm Threshold Scmitt Trigger Hysteresis Vhys Iin Input Current (Vin=0; Vdd=5)* Test Condition Min. 200 200 Cload 20pF 200 200 250 fadck = 250 kHz fadck = 250 kHz 5.6 32.4 36 2/3Vdd 1/3Vdd 0.1 50 0.3 150 1 300 Typ. Max. Unit ns ns ns ns KHz s s s V V V A
* This applies to input pins having an internal pull-up (ENABLE_CHANNEL, LONG_PULSE, SHORT_PULSE)
Selected channel: CH1..CH5 4 s CH0 7 s NB: The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the data 16 bit shift register (signals Serial data, Serial clock) SHIFT REGISTER AND LATCH TIMING Set up time Ta Hold time Tb Serial clock low time Tc Serial clock high time Td Te Serial clock period Latch set up time Tf Tg Latch data high time Long Pulse set_up time with Tset respect to NCEn Long Pulse hold time with Thold respect to NCEn OUTPUTS ELECTRICAL CHARACTERISTICS Iout Output Current (outputs 0..15) DC=33%; preheating DC=66% On Resistance Tj = 25C Rds (ON) Turn on Time (Tdelay + Trise) From 50% Long Pulse to 90% Ton power output rising edge Load = 30 Ohm in parallel with 1.5nF Toff Toff delay time From 50% Long Pulse to 90% power output falling edge Load = 30 Ohm in parallel with 1.5nF
CR LATCH TIMINGS Tls Latch set up time Latch high time Tlhigh Latch data valid to A/D input Tlconv valid delay
100 100
ns ns
50 50 50 50 150 100 100 160 0
ns ns ns ns ns ns ns ns ns
400 1.3 160
mA ns
100
ns
7/16
L6452
DC ELECTRICAL CHARACTERISTICS (Tj = 25C)
Symbol Parameter HEAD ADDRESS SELECTOR OUTPUT Up Counting, Reset Counter, Th Select Channel, Clock Counter and Enable Internal Counter set-up time with respect to Enable channel Tk Up Counting, Reset Counter, Select Channel, Clock Counter and Enable Internal Counter hold time with respect to Enable channel Tj Up Counting with respect to Clock Counter hold time Up counting with respect to Ti Clock Counter set_up time Enable input to active output Tm delay time Clock to active output delay Tn time Disable input to inactive output To delay time Counter Clock Frequency fclk-counter Clock duty cycle ClKdc Turn on/off time Ton/off Test Condition Min. 150 Typ. Max. Unit ns
50
ns
200 100 100 150 100 1 90 325
ns ns ns ns ns MHz % ns
10 From 50% Clock counter or selector signal to 90% of the address output variation Load: see fig. 10
COUNTER TRUTH TABLE Enable internal counter = 1 Up Counting = 1 Reset Counter = 1
Clock Counter 0 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 C1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 C0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0
8/16
L6452
COUNTER TRUTH TABLE (continued) Enable internal counter = 1 Up Counting = 0 Reset Counter = 1
Clock Counter 0 C3 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 C2 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 C0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0
DECODER TRUTH TABLE
OUTPUTS (HS) ACTIVE All inactive 1 2 3 4 5 6 7 8 9 10 11 12 13 All inactive All inactive C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 C0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1
This table is valid for both Channel A and Channel B and when Enable Channel is set to low level.
9/16
L6452
PRINT HEAD TEMPERATURE CONTROL PART Introduction For quality printing, it is necessary to know and control the temperature of the printhead. Thus, the latter has a built - in aluminium resistor, whose value changes slightly with the temperature. The temperature determination is done by injecting a constant current in the resistor, and measuring the voltage drop across it. Since high end printers have two heads, it must also be possible to switch quikly the measurement process from one to the other. The function is foreseen to be integrated into the head driver, and is described hereafter. Print Head Block Diagram (fig. 4) At first we have a constant current source, which can be disabled by an external pin (ONenable) or by a control register, described later. The value of the current can be programmed by an external resistor, and is given by: ICCS = Vref 4 2 Rext
This current is injected either into the aluminium resistor of the head A (Ralu. A) or B (Ralu. B), depending of the switch SW3. The alu. resistors are grounded, and the voltage at their << hot >> side Figure 4. Print Head Block Diagram
(Vx) is re-entered via the pins Vxa and Vxb. Using separate pins from Rxa and Rxb permits to be more flexible, and a filter can eventually be added as shown in the drawing. The voltage Vx is amplified by A1 and A2, and then converted in a digital value. To be compatible with the input range of the A/D converter, it is necessary to subtract an offset voltage Voffset from Vx. Moreover, as the initial value of the alu. resistor is very unprecise. Voffset must be adjustable; this is done by means of a 5 bit - D/A converter, giving 32 different values. Finally, the voltage at the input of the A/D converter is: VCH0 = g1 g2 VX - g2 VOFFSET or VCH0 = g1 g2 Ralu ICCS - g2 VOFFS ET; VOFFSET = VREF/2 + N VREF/32 N = 0, 1, ...31 The reference voltage generator (VREF) is integrated, and used for the current source and both the A/D and D/A converters. In this way, the system performance is independent from the precision of VREF; this one should, however, be stable. Vref is also available on pin #45, and can be used for low consumption purposes. (The external sinked current has to be a DC current) The system is under control of a 10 bit register, CR. CR is accessed serially and has a transparent latch, which can be used or not (by trying the latch signal CR latch to VCC).
VREF Va REF VOLT VREF OUT VREF A1 g1 A A2 + g2 CH0 D CONV START ADCK ADDATA CH5 CH4 + Vx VOFFSET VREF A D/A 5 BIT B D C SW3 CH0_BUF CH3 CH2 CH1 A/D INPUTS
REXT
HIGH-SIDE CONSTANT CURRENT SOURCE SW1 SW2
VREF/2
ONENABLE
LATCH 10 BIT
CRLATCH CONTROL REGISTER CRCLOCK CRDATA
SHIFT REG. 10 BIT A/B ON/OFF DA4 DA3 DA2 DA1 DA0 S2 S1 S0
RXA, RXB
VXA, VXB
ANALOG GND
RALU A
RALU B Note; the analog ground is separated from the digital ground of the remaining part of the driver
D97IN533B
10/16
L6452
Figure 5. Control Register details.
SHIFT DIRECTION
CR9 A/B
CR8 ON/OFF
CR7 DA4
CR6 DA3
CR5 DA2
CR4 DA1
CR3 DA0
CR2 S2
CR1 S1
CR0 S0
SELECTION OF RESISTOR A (A/B = 0) or B (A/B = 0) for TEMPERATURE MEASUREMENT
D/A INPUTS FOR OFFSET COMPENSATION DA0 = LSB DA4 = MSB POSITIVE LOGIC
CHANNEL SELECTION A/D INPUT
D97IN534A
ONE INTERNAL CHANNEL (VX MEASUREMENT) FIVE UNCOMMITTED, GENRAL-PURPOSE EXTERNAL CHANNELS
SWITCHES THE CURRENT SOURCE ON or OFF; LINKED WITH ONENABLE INPUT PIN
S2 S1 S0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
SELECTED CHANNEL
0 (INTERNAL) 1 (EXTERNAL) 2 (EXTERNAL) 3 (EXTERNAL) 4 (EXTERNAL) 5 (EXTERNAL) 6 7
CH0 BUF
A B B B B B C D
ON/OFF
0 1 0 1
ONENABLE
1 1 0 0
ACTION
OFF OFF OFF ON
Figure 6. CR Latch Timings
CRDATA DA0 S2 S1 S0
CRCLOCK
tls tlhigh
CRLATCH
tlconv
CONVSTART
D97IN535
Figure 7. A/D Converter Timings
CONVSTART
ADCK
ADDATA
HIGH IMPEDANCE
t cscks tcsckh
7
t ckout
6
5
4
3
2
1
0
HIGH IMPEDANCE
D97IN536
tcsx
11/16
L6452
Figure 8. Power Output Timing
LONG PULSE or SHORT PULSE
50%
50%
90%
90%
POWER OUTPUT 10% td tr td tf 10%
D97IN526
Figure 9. Trigger of Nozzle Check Signal
VPOWER FROM THE COMMON CONNECTION OF ANALOG MULTIPLEXERS
VLOGIC NOZZLE CHECK OUTPUT
+
1
0 INTERNAL REFERENCE NCEM
HSA/B SHORT CIRCUIT DETECTION
D97IN527
12/16
L6452
Figure 10. Address Output Timing
200 HS OUTPUT 250pF A
CLOCK SIGNAL COUNTER SEL 0 to 3 50% 50% SELECTOR SIGNAL
90%
90%
ADDRESS OUTPUT MEASURED AT POINT A
10% td tr td tf
10%
D97IN528A
Figure 11. Mode Counter
UP COUNTING
RESET COUNTER
SELECT CHANNEL
ENABLE INTERNAL COUNTER
CLOCK COUNTER
ti tj
ENABLE CHANNEL
tk th
OUTPUT 1 :13 HSA or HSB)
tm tn
D97IN529A
to
13/16
L6452
Figure 12. Mode Sel 0:3
SEL 0:3
SELECT CHANNEL
ENABLE INTERNAL COUNTER
ENABLE CHANNEL
tk th
OUTPUT 1 :13 HSA or HSB)
tm tn
D97IN530
to
Figure 13. Sequence of Shift Register Data Loading
SERIAL DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SERIAL CLOCK LATCH DATA LONG PULSE SHORT PULSE OUTPUT * OUTPUT ** * THE CORRESPONDING DATA BIT IS SET ** THE CORRESPONDING DATA BIT IS RESET
D97IN531
Figure 14. Latch Timing
ta tb
SERIAL DATA
SERIAL CLOCK
LATCH DATA
tf tc
D97IN532
tg td
te
14/16
L6452
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90
mm TYP. MAX. 3.40 0.010 2.80 3.05 0.38 0.23 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 0(min.), 7(max.) 0.95 0.026 17.45 14.10 0.667 0.547 23.45 20.10 0.100 0.0087 0.005 0.903 0.783 MIN.
inch TYP. MAX. 0.134
OUTLINE AND MECHANICAL DATA
0.110
0.120 0.015 0.009
0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063
0.923 0.791
0.687 0.555
0.037
PQFP100
15/16
L6452
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
16/16

▲Up To Search▲

Price & Availability of L6452

	To Download L6452 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .